NXP Semiconductors KL25 Series - Chapter 34; RTC Signal Descriptions

34.1.3 RTC Signal Descriptions
Table 34-1. RTC signal descriptions
Signal Description I/O
RTC_CLKOUT 1 Hz square-wave output O
34.1.3.1 RTC clock output
The clock to the seconds counter is available on the RTC_CLKOUT signal. It is a 1 Hz
square wave output.
34.2 Register definition
All registers must be accessed using 32-bit writes and all register accesses incur three
wait states.
Write accesses to any register by non-supervisor mode software, when the supervisor
access bit in the control register is clear, will terminate with a bus error.
Read accesses by non-supervisor mode software complete as normal.
Writing to a register protected by the lock register does not generate a bus error, but the
write will not complete.
RTC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_D000 RTC Time Seconds Register (RTC_TSR) 32 R/W 0000_0000h 34.2.1/599
4003_D004 RTC Time Prescaler Register (RTC_TPR) 32 R/W 0000_0000h 34.2.2/599
4003_D008 RTC Time Alarm Register (RTC_TAR) 32 R/W 0000_0000h 34.2.3/600
4003_D00C RTC Time Compensation Register (RTC_TCR) 32 R/W 0000_0000h 34.2.4/600
4003_D010 RTC Control Register (RTC_CR) 32 R/W 0000_0000h 34.2.5/601
4003_D014 RTC Status Register (RTC_SR) 32 R/W 0000_0001h 34.2.6/603
4003_D018 RTC Lock Register (RTC_LR) 32 R/W 0000_00FFh 34.2.7/604
4003_D01C RTC Interrupt Enable Register (RTC_IER) 32 R/W 0000_0007h 34.2.8/605
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
598 Freescale Semiconductor, Inc.