NXP Semiconductors KL25 Series - Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration

• NVICIPR2[23:22]
3.3.3 Asynchronous wake-up interrupt controller (AWIC)
configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at www.arm.com.
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Nested vectored
interrupt controller
(NVIC)
Wake-up
requests
Module
Module
Clock logic
Figure 3-3. Asynchronous wake-up interrupt controller configuration
Table 3-9. Reference links to related information
Topic Related module Reference
System memory map System memory map
Clocking Clock distribution
Power management Power management
Nested vectored
interrupt controller
(NVIC)
NVIC
Wake-up requests AWIC wake-up sources
3.3.3.1 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-10. AWIC stop wake-up sources
Wake-up source Description
Available system resets RESET pin when LPO is its clock source
Low-voltage detect Mode Controller
Low-voltage warning Mode Controller
Pin interrupts Port control module - Any enabled pin interrupt is capable of waking the system
ADC The ADC is functional when using internal clock source
Table continues on the next page...
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 55