To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin
data clear, and pin data toggle registers exist to allow one or more outputs within one port
to be set, cleared, or toggled from a single register write.
The corresponding Port Control and Interrupt module does not need to be enabled to
update the state of the port data direction registers and port data output registers including
the set/clear/toggle registers.
41.4.3 IOPORT
The GPIO registers are also aliased to the IOPORT interface on the Cortex-M0+ from
address $F800_0000. Accesses via the IOPORT interface occur in parallel with any
instruction fetches and will therefore complete in a single cycle. If the DMA attempts to
access the GPIO registers on the same cycle as an IOPORT access, then the DMA access
will stall until any IOPORT accesses have completed.
During Compute Operation, the GPIO registers remain accessible via the IOPORT
interface only. Since the clocks to the Port Control and Interrupt modules are disabled
during Compute Operation, the Pin Data Input Registers do not update with the current
state of the pins.
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
784 Freescale Semiconductor, Inc.
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