• Configurable sample time and conversion speed/power
• Conversion complete/hardware average complete flag and interrupt
• Input clock selectable from up to four sources
• Operation in Low-Power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the clock
• Selectable hardware conversion trigger with hardware channel select
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function
• Selectable voltage reference: external or alternate
• Self-Calibration mode
28.1.2 Block diagram
The following figure is the ADC module block diagram.
Introduction
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
458 Freescale Semiconductor, Inc.
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