17.1.1 Overview
The following figure is a generic block diagram of the processor core and platform for
this class of ultra low-end microcontrollers.
AXBS
CM0+ Core Platform
FMC
LD/ST
Dbg
NVIC
Fetch
Cortex-M0+ Core
MTB Port
AHB Bus
AGU
MUL
RAM
Array
32
Dec Rn
SHFT
ALU
DMA_4ch
NVM
Array
PRAM
32
RGPIO
PBRIDGE
BME
32
IO Port
Slave
Peripherals
Alt-Master
-Lite
m0
s1
s2
s0
m3
m2
Note: BME can be accessed only by the core.
Figure 17-1. Generic Cortex-M0+ core platform block diagram
As shown in the block diagram, the BME module interfaces to a crossbar switch AHB
slave port as its primary input and sources an AHB bus output to the Peripheral Bridge
(PBRIDGE) controller. The BME hardware microarchitecture is a 2-stage pipeline design
matching the protocol of the AMBA-AHB system bus interfaces. The PBRIDGE module
converts the AHB system bus protocol into the IPS/APB protocol used by the attached
slave peripherals.
17.1.2 Features
The key features of the BME include:
• Lightweight implementation of decorated storage for peripheral address space
• Additional access semantics encoded into the reference address
Introduction
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
272 Freescale Semiconductor, Inc.
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