Table 24-18. MCG modes of operation (continued)
Mode Description
Bypassed Low Power
External (BLPE)
Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C2[LP] bit is written to 1
In BLPE mode, MCGOUTCLK is derived from the external reference clock. The FLL is disabled and
PLL is disabled even if the C5[PLLCLKEN0] is set to 1.
Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power
mode assignments, see the chapter that describes how modules are configured and MCG behavior
during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static
except in the following case:
MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1
MCGIRCLK is active in Normal Stop mode when all the following conditions become true:
• C1[IRCLKEN] = 1
• C1[IREFSTEN] = 1
NOTE: • In VLPS Stop Mode, the MCGIRCLK can be programmed to stay enabled and
continue running if C1[IRCLKEN] = 1, C1[IREFSTEN]=1, and Fast IRC clock is
selected (C2[IRCS] = 1)
NOTE: • When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the
MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be
configured to 2’b10if entering from PEE mode or to 2’b01 if entering from PEI mode,
C5[PLLSTEN0] will be force to 1'b0 and S[LOCK0] bit will be cleared without setting
S[LOLS0].
• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN0]=0, on exit
the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be
configured to 2’b10 and S[LOCK0] bit will clear without setting S[LOLS0]. If
C5[PLLSTEN0]=1, the S[LOCK0] bit will not get cleared and on exit the MCG will
continue to run in PEE mode.
1. If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected
(C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode
switch to a non low power clock mode must be avoided.
NOTE
For the chip-specific modes of operation, see the power
management chapter of this MCU.
24.4.1.2 MCG mode switching
The C1[IREFS] bit can be changed at any time, but the actual switch to the newly
selected reference clocks is shown by the S[IREFST] bit. When switching between
engaged internal and engaged external modes, the FLL will begin locking again after the
switch is completed.
Chapter 24 Multipurpose Clock Generator (MCG)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 387
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