11.5.1 Pin Control Register n (PORTx_PCRn)
NOTE
Refer to the Signal Multiplexing and Signal Descriptions
chapter for the reset value of this device.
See the GPIO Configuration section for details on the available
functions for each pin.
Do not modify pin configuration registers associated with pins
not available in your selected package. All un-bonded pins not
available in your package will default to DISABLE state for
lowest power consumption.
Address: Base address + 0h offset + (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 ISF 0
IRQC
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MUX
0
DSE
0
PFE
0
SRE PE PS
W
Reset
0 0 0 0 0 x* x* x* 0 x* 0 x* 0 x* x* x*
* Notes:
x = Undefined at reset.•
PORTx_PCRn field descriptions
Field Description
31–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24
ISF
Interrupt Status Flag
This bit is read only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
Table continues on the next page...
Chapter 11 Port control and interrupts (PORT)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 183
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