Address: 4003_7000h base + 0h offset = 4003_7000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
Reserved
MDIS FRZ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
PIT_MCR field descriptions
Field Description
0–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29
Reserved
This field is reserved.
30
MDIS
Module Disable - (PIT section)
Disables the standard timers. The RTI timer is not affected by this field. This field must be enabled before
any other setup is done.
0 Clock for standard PIT timers is enabled.
1 Clock for standard PIT timers is disabled.
31
FRZ
Freeze
Allows the timers to be stopped when the device enters the Debug mode.
0 Timers continue to run in Debug mode.
1 Timers are stopped in Debug mode.
Memory map/register description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
576 Freescale Semiconductor, Inc.
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