NXP Semiconductors KL25 Series - Port Set Output Register (Gpiox_Psor)

41.2.2 Port Set Output Register (GPIOx_PSOR)
This register configures whether to set the fields of the PDOR.
Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
PTSO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PSOR field descriptions
Field Description
31–0
PTSO
Port Set Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to logic 1.
41.2.3 Port Clear Output Register (GPIOx_PCOR)
This register configures whether to clear the fields of PDOR.
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
PTCO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PCOR field descriptions
Field Description
31–0
PTCO
Port Clear Output
Writing to this register will update the contents of the corresponding bit in the Port Data Output Register
(PDOR) as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is cleared to logic 0.
Memory map and register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
776 Freescale Semiconductor, Inc.