NXP Semiconductors KL25 Series - Bit Address

Table 38-41. I2C divider and hold values (continued)
ICR
(hex)
SCL
divider
SDA hold
value
SCL hold
(start)
value
SCL hold
(stop)
value
ICR
(hex)
SCL
divider
(clocks)
SDA hold
(clocks)
SCL hold
(start)
value
SCL hold
(stop)
value
14 80 17 34 41 34 1152 193 574 577
15 88 17 38 45 35 1280 193 638 641
16 104 21 46 53 36 1536 257 766 769
17 128 21 58 65 37 1920 257 958 961
18 80 9 38 41 38 1280 129 638 641
19 96 9 46 49 39 1536 129 766 769
1A 112 17 54 57 3A 1792 257 894 897
1B 128 17 62 65 3B 2048 257 1022 1025
1C 144 25 70 73 3C 2304 385 1150 1153
1D 160 25 78 81 3D 2560 385 1278 1281
1E 192 33 94 97 3E 3072 513 1534 1537
1F 240 33 118 121 3F 3840 513 1918 1921
38.4.2 10-bit address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.
Various combinations of read/write formats are possible within a transfer that includes
10-bit addressing.
38.4.2.1 Master-transmitter addresses a slave-receiver
The transfer direction is not changed. When a 10-bit address follows a START condition,
each slave compares the first 7 bits of the first byte of the slave address (11110XX) with
its own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that
more than one device finds a match and generates an acknowledge (A1). Each slave that
finds a match compares the 8 bits of the second byte of the slave address with its own
address, but only one slave finds a match and generates an acknowledge (A2). The
matching slave remains addressed by the master until it receives a STOP condition (P) or
a repeated START condition (Sr) followed by a different slave address.
Chapter 38 Inter-Integrated Circuit (I2C)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 707