Table 3-45. Reference links to related information (continued)
Topic Related module Reference
Signal Multiplexing Port control Signal Multiplexing
3.9.2.1 SPI Instantiation Information
This device contains two SPI module that supports 8-bit data length.
SPI0 is clocked on the bus clock. SPI1 is clocked from the system clock. SPI1 is
therefore disabled in "Partial Stop Mode".
The SPI supports DMA request and can operate in VLPS mode. When the SPI is
operating in VLPS mode, it will operate as a slave.
SPI can wakeup MCU from VLPS mode upon reception of SPI data in slave mode.
3.9.3 I2C Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Register
access
Peripheral
bridge
Module signals
2
I C
Figure 3-35. I2C configuration
Table 3-46. Reference links to related information
Topic Related module Reference
Full description I
2
C I
2
C
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 97
To Next Page
Loading...
