CMPx_SCR field descriptions (continued)
Field Description
0 Interrupt is disabled.
1 Interrupt is enabled.
3
IEF
Comparator Interrupt Enable Falling
Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is
set.
0 Interrupt is disabled.
1 Interrupt is enabled.
2
CFR
Analog Comparator Flag Rising
Detects a rising-edge on COUT, when set, during normal operation. CFR is cleared by writing 1 to it.
During Stop modes, CFR is level sensitive .
0 Rising-edge on COUT has not been detected.
1 Rising-edge on COUT has occurred.
1
CFF
Analog Comparator Flag Falling
Detects a falling-edge on COUT, when set, during normal operation. CFF is cleared by writing 1 to it.
During Stop modes, CFF is level senstive .
0 Falling-edge on COUT has not been detected.
1 Falling-edge on COUT has occurred.
0
COUT
Analog Comparator Output
Returns the current value of the Analog Comparator output, when read. The field is reset to 0 and will read
as CR1[INV] when the Analog Comparator module is disabled, that is, when CR1[EN] = 0. Writes to this
field are ignored.
29.7.5 DAC Control Register (CMPx_DACCR)
Address: 4007_3000h base + 4h offset = 4007_3004h
Bit 7 6 5 4 3 2 1 0
Read
DACEN VRSEL VOSEL
Write
Reset
0 0 0 0 0 0 0 0
CMPx_DACCR field descriptions
Field Description
7
DACEN
DAC Enable
Enables the DAC. When the DAC is disabled, it is powered down to conserve power.
0 DAC is disabled.
1 DAC is enabled.
6
VRSEL
Supply Voltage Reference Source Select
Table continues on the next page...
Memory map/register definitions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
518 Freescale Semiconductor, Inc.
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