NXP Semiconductors KL25 Series - MDM-AP Status Register

Table 9-3. MDM-AP Control register assignments (continued)
Bit Name Secure
1
Description
2 Debug Request N Set to force the core to halt.
If the core is in a stop or wait mode, this bit can be used to wakeup the
core and transition to a halted state.
3 System Reset Request Y Set to force a system reset. The system remains held in reset until this
bit is cleared.
4 Core Hold Reset N Configuration bit to control core operation at the end of system reset
sequencing.
0 Normal operation - release the core from reset along with the rest of
the system at the end of system reset sequencing.
1 Suspend operation - hold the core in reset at the end of reset
sequencing. Once the system enters this suspended state, clearing
this control bit immediately releases the core from reset and CPU
operation begins.
5 VLLSx Debug Request
(VLLDBGREQ)
N Set to configure the system to be held in reset after the next recovery
from a VLLSx mode. This bit is ignored on a VLLS wakeup via the
Reset pin. During a VLLS wakeup via the Reset pin, the system can be
held in reset by holding the reset pin asserted allowing the debugger to
re-initialize the debug modules.
This bit holds the system in reset when VLLSx modes are exited to
allow the debugger time to re-initialize debug IP before the debug
session continues.
The Mode Controller captures this bit logic on entry to VLLSx modes.
Upon exit from VLLSx modes, the Mode Controller will hold the system
in reset until VLLDBGACK is asserted.
The VLLDBGREQ bit clears automatically due to the POR reset
generated as part of the VLLSx recovery.
6 VLLSx Debug Acknowledge
(VLLDBGACK)
N Set to release a system being held in reset following a VLLSx recovery
This bit is used by the debugger to release the system reset when it is
being held on VLLSx mode exit. The debugger re-initializes all debug
IP and then assert this control bit to allow the Mode Controller to
release the system from reset and allow CPU operation to begin.
The VLLDBGACK bit is cleared by the debugger or can be left set
because it clears automatically due to the POR reset generated as part
of the next VLLSx recovery.
7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge the DAP LLS and VLLS Status bits have
been read. This acknowledge automatically clears the status bits.
This bit is used by the debugger to clear the sticky LLS and VLLSx
mode entry status bits. This bit is asserted and cleared by the
debugger.
8 –
31
Reserved for future use N
1. Command available in secure mode
SWD status and control registers
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
154 Freescale Semiconductor, Inc.