NXP Semiconductors KL25 Series - Compare Value Registers (Adcx_Cvn)

Table 28-43. Data result register description (continued)
Conversion
mode
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format
10-bit single-
ended
0 0 0 0 0 0 D D D D D D D D D D Unsigned right-
justified
9-bit differential S S S S S S S S D D D D D D D D Sign-extended
2's complement
8-bit single-
ended
0 0 0 0 0 0 0 0 D D D D D D D D Unsigned right-
justified
NOTE
S: Sign bit or sign bit extension;
D: Data, which is 2's complement data if indicated
Address: 4003_B000h base + 10h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 D
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_Rn field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
D
Data result
28.3.5 Compare Value Registers (ADCx_CVn)
The compare value registers (CV1 and CV2) contain a compare value used to compare
the conversion result when the compare function is enabled, that is, SC2[ACFE]=1. This
register is formatted in the same way as the Rn registers in different modes of operation
for both bit position definition and value format using unsigned or sign-extended 2's
complement. Therefore, the compare function uses only the CVn fields that are related to
the ADC mode of operation.
The compare value 2 register (CV2) is used only when the compare range function is
enabled, that is, SC2[ACREN]=1.
Chapter 28 Analog-to-Digital Converter (ADC)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 469