15.2 LLWU signal descriptions
The signal properties of LLWU are shown in the following table. The external wakeup
input pins can be enabled to detect either rising-edge, falling-edge, or on any change.
Table 15-1. LLWU signal descriptions
Signal Description I/O
LLWU_Pn Wakeup inputs (n = 0-15) I
15.3 Memory map/register definition
The LLWU includes the following registers:
• Five 8-bit wakeup source enable registers
• Enable external pin input sources
• Enable internal peripheral sources
• Three 8-bit wakeup flag registers
• Indication of wakeup source that caused exit from a low-leakage power mode
includes external pin or internal module interrupt
• Two 8-bit wakeup pin filter enable registers
NOTE
The LLWU registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
All LLWU registers are reset by Chip Reset not VLLS and by
reset types that trigger Chip Reset not VLLS. Each register's
displayed reset value represents this subset of reset types.
LLWU registers are unaffected by reset types that do not trigger
Chip Reset not VLLS. For more information about the types of
reset on this chip, refer to the Introduction details.
LLWU signal descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
248 Freescale Semiconductor, Inc.
To Next Page
Loading...
