NXP Semiconductors KL25 Series - Internal Clocking Requirements; Clock Divider Values after Reset

Table 5-1. Clock Summary (continued)
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
UART0 clock Up to 48 MHz Up to 4 MHz MCGIRCLK,
MCGPLLCLK/2,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[UART0SR
C]=00 or selected clock
source disabled.
USB FS clock 48 MHz N/A MCGPLLCLK/2 or
MCGFLLCLK, or
USB_CLKIN
USB FS OTG is
disabled
1. If in BLPI mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency
needs to be limited to 800 kHz if executing from flash.
5.5 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. The
following requirements must be met when configuring the clocks for this device:
1. The core, platform, and system clock are programmable from a divide-by-1 through
divide-by-16 setting. The core, platform, and system clock frequencies must be 48
MHz or slower.
2. The bus clock and flash clock frequency is divided from the system clock and is
programmable from a divide-by-1 through divide-by-8 setting. The bus clock and
flash clock must be programmed to 24 MHz or slower.
The following is a common clock configuration for this device:
Clock Frequency
Core clock 48 MHz
Platform clock 48 MHz
System clock 48 MHz
Bus clock 24 MHz
Flash clock 24 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the SIM module’s CLKDIV1 registers. Two bits in
the flash memory's FTFA_FOPT register controls the reset value of the core clock,
system clock, bus clock, and flash clock dividers as shown below:
Chapter 5 Clock Distribution
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 119