SW-DP
SELECT[31:24] (APSEL) selects the AP
SELECT[7:4] (APBANKSEL) selects the bank
A[3:2] from the APACC selects the register
within the bank
AHB Access Port
(AHB-AP)
MDM-AP
Status
0x00
Control
0x01
IDR
0x3F
AHB-AP
SELECT[31:24] = 0x00 selects the AHB-AP
See ARM documentation for further details
MDM-AP
SELECT[31:24] = 0x01 selects the MDM-AP
SELECT[7:4] = 0x0 selects the bank with Status and Ctrl
A[3:2] = 2’b00 selects the Status Register
A[3:2] = 2’b01 selects the Control Register
SELECT[7:4] = 0xF selects the bank with IDR
A[3:2] = 2’b11 selects the IDR Register
(IDR register reads 0x001C_0020)
Bus Matrix
See Control and Status Register
Descriptions
Debug PortInternal BusAccess Port
Data[31:0] A[7:4] A[3:2] RnW
APSEL
Decode
Debug Port ID Register (IDCODE)
Control/Status (CTRL/STAT)
AP Select (SELECT)
Read Buffer (RDBUFF)
DP Registers
0x00
0x04
0x08
0x0C
Data[31:0] A[3:2] RnW
DPACC
Data[31:0] A[3:2] RnW
APACC
Debug Port
(DP)
Generic
See the ARM Debug Interface v5p1 Supplement.
Figure 9-1. MDM AP Addressing
9.3.1 MDM-AP Control Register
Table 9-3. MDM-AP Control register assignments
Bit Name Secure
1
Description
0 Flash Mass Erase in Progress Y Set to cause mass erase. Cleared by hardware after mass erase
operation completes.
When mass erase is disabled (via MEEN and SEC settings), the erase
request does not occur and the Flash Mass Erase in Progress bit
continues to assert until the next system reset.
1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set it
overrides the C_DEBUGEN bit within the DHCSR and force disables
Debug logic.
Table continues on the next page...
Chapter 9 Debug
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 153
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