NXP Semiconductors KL25 Series - UART Data Register (Uartx_D)

40.2.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only
receive data buffer and writes go to the write-only transmit data buffer. Reads and writes
of this register are also involved in the automatic flag clearing mechanisms for the UART
status flags.
Address: Base address + h offset
Bit 7 6 5 4 3 2 1 0
Read
R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0
Write
Reset
0 0 0 0 0 0 0 0
UARTx_D field descriptions
Field Description
7
R7T7
Read receive data buffer 7 or write transmit data buffer 7.
6
R6T6
Read receive data buffer 6 or write transmit data buffer 6.
5
R5T5
Read receive data buffer 5 or write transmit data buffer 5.
4
R4T4
Read receive data buffer 4 or write transmit data buffer 4.
3
R3T3
Read receive data buffer 3 or write transmit data buffer 3.
2
R2T2
Read receive data buffer 2 or write transmit data buffer 2.
1
R1T1
Read receive data buffer 1 or write transmit data buffer 1.
0
R0T0
Read receive data buffer 0 or write transmit data buffer 0.
40.2.9 UART Control Register 4 (UARTx_C4)
Address: Base address + h offset
Bit 7 6 5 4 3 2 1 0
Read
TDMAS
0
RDMAS
0 0 0
Write
Reset
0 0 0 0 0 0 0 0
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
760 Freescale Semiconductor, Inc.