NXP Semiconductors KL25 Series - Chapter 5; Introduction; Programming Model; High-Level Device Clocking Diagram

Chapter 5
Clock Distribution
5.1 Introduction
This chapter presents the clock architecture for the device, the overview of the clocks and
includes a terminology section.
The Cortex M0+ resides within a synchronous core platform, where the processor and
bus masters, Flash and peripherals clocks can be configured independently. The clock
distribution figure shows how clocks from the MCG and XOSC modules are distributed
to the microcontroller’s other function units. Some modules in the microcontroller have
selectable clock input.
5.2 Programming model
The selection and multiplexing of system clock sources is controlled and programmed via
the MCG module. The setting of clock dividers and module clock gating for the system
are programmed via the SIM module. Reference those sections for detailed register and
bit descriptions.
5.3 High-Level device clocking diagram
The following system oscillator, MCG, and SIM module registers control the
multiplexers, dividers, and clock gates shown in the below figure:
OSC MCG SIM
Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2
Dividers — MCG_Cx SIM_CLKDIVx
Clock gates OSC_CR MCG_C1 SIM_SCGCx
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 115