NXP Semiconductors KL25 Series - KL25 Sub-Family Reference Manual, Rev. 3, September

The cache in flash controller is enabled and caching both instruction and data type fetches
after reset. It is possible to have these states for the cache:
DFCC DFCIC DFCDA Description
0 0 0 Cache is on for both
instruction and data.
0 0 1 Cache is on for instruction
and off for data.
0 1 0 Cache is off for instruction
and on for data.
0 1 1 Cache is off for both
instruction and data.
1 X X Cache is off.
Address: F000_3000h base + Ch offset = F000_300Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
ESFC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DFCS
EFDS
DFCC
DFCIC
DFCDA
0
ARB
0
W
CFCC
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_PLACR field descriptions
Field Description
31–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
ESFC
Enable Stalling Flash Controller
This field is used to enable stalling flash controller when flash is busy.
0 Disable stalling flash controller when flash is busy.
1 Enable stalling flash controller when flash is busy.
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Memory map/register descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
294 Freescale Semiconductor, Inc.