SMC_PMCTRL field descriptions (continued)
Field Description
2–0
STOPM
Stop Mode Control
When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is
entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled
using the PMPROT register. After any system reset, this field is cleared by hardware on any successful
write to the PMPROT register.
NOTE: When set to VLLSx, the VLLSM bits in the STOPCTRL register is used to further select the
particular VLLS submode which will be entered.
NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial
Stop mode if desired.
000 Normal Stop (STOP)
001 Reserved
010 Very-Low-Power Stop (VLPS)
011 Low-Leakage Stop (LLS)
100 Very-Low-Leakage Stop (VLLSx)
101 Reserved
110 Reseved
111 Reserved
13.3.3 Stop Control Register (SMC_STOPCTRL)
The STOPCTRL register provides various control bits allowing the user to fine tune
power consumption during the stop mode selected by the STOPM field.
NOTE
This register is reset on Chip POR not VLLS and by reset types
that trigger Chip POR not VLLS. It is unaffected by reset types
that do not trigger Chip POR not VLLS. See the Reset section
details for more information.
Address: 4007_E000h base + 2h offset = 4007_E002h
Bit 7 6 5 4 3 2 1 0
Read
PSTOPO PORPO
0 0
VLLSM
Write
Reset
0 0 0 0 0 0 1 1
SMC_STOPCTRL field descriptions
Field Description
7–6
PSTOPO
Partial Stop Option
These bits control whether a Partial Stop mode is entered when STOPM=STOP. When entering a Partial
Stop mode from RUN mode, the PMC, MCG and flash remain fully powered, allowing the device to
wakeup almost instantaneously at the expense of higher power consumption. In PSTOP2, only system
Table continues on the next page...
Memory map and register descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
222 Freescale Semiconductor, Inc.
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