NXP Semiconductors KL25 Series - 3.6 Memories and Memory Interfaces; 3.6.1 Flash Memory Configuration

Memories and Memory Interfaces
3.6.1 Flash Memory Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register
access
Flash memory
Transfers
Flash memory
controller
Peripheral bus
controller 0
Figure 3-16. Flash memory configuration
Table 3-26. Reference links to related information
Topic Related module Reference
Full description Flash memory Flash memory
System memory map System memory map
Clocking Clock Distribution
Transfers Flash memory
controller
Flash memory controller
Register access Peripheral bridge Peripheral bridge
3.6.1.1 Flash Memory Sizes
The devices covered in this document contain 1 program flash block consisting of 1 KB
sectors.
The amounts of flash memory for the devices covered in this document are:
Table 3-27. KL25 flash memory size
Device Program flash (KB) Block 0 (P-Flash) address range
MKL25Z32VFM4 32 0x0000_0000 – 0x0000_7FFF
MKL25Z64VFM4 64 0x0000_0000 – 0x0000_FFFF
Table continues on the next page...
3.6
Memories and Memory Interfaces
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
72 Freescale Semiconductor, Inc.