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NXP Semiconductors KL25 Series - Freescale Semiconductor, Inc

NXP Semiconductors KL25 Series
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DMA_DCRn field descriptions (continued)
Field Description
1010 Circular buffer size is 8 KB
1011 Circular buffer size is 16 KB
1100 Circular buffer size is 32 KB
1101 Circular buffer size is 64 KB
1110 Circular buffer size is 128 KB
1111 Circular buffer size is 256 KB
7
D_REQ
Disable request
DMA hardware automatically clears the corresponding DCRn[ERQ] bit when the byte count register
reaches zero.
0 ERQ bit is not affected.
1 ERQ bit is cleared when the BCR is exhausted.
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–4
LINKCC
Link channel control
Allows DMA channels to have their transfers linked. The current DMA channel triggers a DMA request to
the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits.
If not in cycle steal mode (DCRn[CS]=0) and LINKCC equals 01 or 10, no link to LCH1 occurs.
If LINKCC equals 01, a link to LCH1 is created after each cycle-steal transfer performed by the current
DMA channel is completed. As the last cycle-steal is performed and the BCR reaches zero, then the link to
LCH1 is closed and a link to LCH2 is created.
00 No channel-to-channel linking
01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the
BCR decrements to zero
10 Perform a link to channel LCH1 after each cycle-steal transfer
11 Perform a link to channel LCH1 after the BCR decrements to zero
3–2
LCH1
Link channel 1
Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as
the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
1–0
LCH2
Link channel 2
Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as
the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
Memory Map and Registers
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
360 Freescale Semiconductor, Inc.

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