NXP Semiconductors KL25 Series - SPI Control Register 2 (Spix_C2)

SPI0_C1 field descriptions (continued)
Field Description
0
LSBFE
LSB first (shifter direction)
This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data
register always have the MSB in bit 7.
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
37.3.2 SPI control register 2 (SPIx_C2)
This read/write register is used to control optional features of the SPI system. Bit 6 is not
implemented and always reads 0.
Address: 4007_6000h base + 1h offset = 4007_6001h
Bit 7 6 5 4 3 2 1 0
Read
SPMIE Reserved TXDMAE MODFEN BIDIROE RXDMAE SPISWAI SPC0
Write
Reset
0 0 0 0 0 0 0 0
SPI0_C2 field descriptions
Field Description
7
SPMIE
SPI match interrupt enable
This is the interrupt enable bit for the SPI receive data buffer hardware match (SPMF) function.
0 Interrupts from SPMF inhibited (use polling)
1 When SPMF is 1, requests a hardware interrupt
6
Reserved
This field is reserved.
Do not write to this reserved bit.
5
TXDMAE
Transmit DMA enable
This bit enables a transmit DMA request. When this bit is set to 1, a transmit DMA request is asserted
when both SPTEF and SPE are set, and the interrupt from SPTEF is disabled.
0 DMA request for transmit is disabled and interrupt from SPTEF is allowed
1 DMA request for transmit is enabled and interrupt from SPTEF is disabled
4
MODFEN
Master mode-fault function enable
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave
select input.) In master mode, this bit determines how the SS pin is used. For details, refer to the
description of the SSOE bit in the C1 register.
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Table continues on the next page...
Chapter 37 Serial Peripheral Interface (SPI)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 663