NXP Semiconductors KL25 Series - 11.6.3 External interrupts

11.6.2 Global pin control
The two global pin control registers allow a single register write to update the lower half
of the pin control register on up to sixteen pins, all with the same value.
The global pin control registers are designed to enable software to quickly configure
multiple pins within the one port for the same peripheral function. However, the interrupt
functions cannot be configured using the global pin control registers.
The global pin control registers are write-only registers, that always read as zero.
11.6.3 External interrupts
The external interrupt capability of the PORT module is available in all digital pin
muxing modes provided the PORT module is enabled.
Each pin can be individually configured for any of the following external interrupt
modes:
• Interrupt disabled, default out of reset
• Active high level sensitive interrupt
• Active low level sensitive interrupt
• Rising edge sensitive interrupt
• Falling edge sensitive interrupt
• Rising and falling edge sensitive interrupt
• Rising edge sensitive DMA request
• Falling edge sensitive DMA request
• Rising and falling edge sensitive DMA request
The interrupt status flag is set when the configured edge or level is detected on the output
of the pin. When not in Stop mode, the input is first synchronized to the bus clock to
detect the configured level or edge transition.
The PORT module generates a single interrupt that asserts when the interrupt status flag
is set for any enabled interrupt for that port. The interrupt negates after the interrupt status
flags for all enabled interrupts have been cleared by writing a logic 0 to the ISF flag in
the PORT_PCRn register.
The PORT module generates a single DMA request that asserts when the interrupt status
flag is set for any enabled DMA request in that port. The DMA request negates after the
DMA transfer is completed, because that clears the interrupt status flags for all enabled
DMA requests.
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
188 Freescale Semiconductor, Inc.