NXP Semiconductors KL25 Series - 3.8.3 Low-power timer configuration

Table 3-40. PIT channel assignments for periodic DMA triggering
PIT Channel DMA Channel Number
PIT Channel 0 DMA Channel 0
PIT Channel 1 DMA Channel 1
3.8.2.2 PIT/ADC Triggers
PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits
in the SIM module. For more details, refer to SIM chapter.
3.8.2.3 PIT/TPM Triggers
PIT triggers are selected as TPMx trigger sources using the TPMx_CONF[TRGSEL] bits
in the TPM module. For more details, refer to TPM chapter.
3.8.2.4 PIT/DAC Triggers
PIT Channel 0 is configured as the DAC hardware trigger source. For more details, refer
to DAC chapter.
3.8.3 Low-power timer configuration
Signal multiplexing
Register
access
Peripheral
bridge
Module signals
Low-power timer
Figure 3-26. LPT configuration
Table 3-41. Reference links to related information
Topic Related module Reference
Full description Low-power timer Low-power timer
Table continues on the next page...
Timers
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
88 Freescale Semiconductor, Inc.