Chapter 23
DMA Controller Module
23.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration information.
This chapter describes the direct memory access (DMA) controller module. It provides an
overview of the module and describes in detail its signals and programming model. The
latter sections of this chapter describe operations, features, and supported data transfer
modes in detail.
Note
The designation n is used throughout this section to refer to
registers or signals associated with one of the four identical
DMA channels: DMA0, DMA1, DMA2, or DMA3.
23.1.1 Overview
The DMA controller module enables fast transfers of data, providing an efficient way to
move blocks of data with minimal processor interaction. The DMA module, shown in the
following figure, has four channels that allow 8-bit, 16-bit, or 32-bit data transfers. Each
channel has a dedicated source address register (SARn), destination address register
(DARn), status register (DSRn), byte count register (BCRn), and control register
(DCRn). Collectively, the combined program-visible registers associated with each
channel define a transfer control descriptor (TCD). All transfers are dual address, moving
data from a source memory location to a destination memory location with the module
operating as a 32-bit bus master connected to the system bus. The programming model is
accessed through a 32-bit connection with the slave peripheral bus. DMA data transfers
may be explicitly initiated by software or by peripheral hardware requests.
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 349
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