Table 4-1. System memory map (continued)
System 32-bit Address Range Destination Slave Access
0xF000_1000–0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core
0xF000_2000–0xF000_2FFF ROM table Cortex-M0+ core
0xF000_3000–0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core
0xF000_4000–0xF7FF_FFFF Reserved –
0xF800_0000–0xFFFF_FFFF IOPORT: GPIO (single cycle) Cortex-M0+ core
1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of
flash implemented for a particular device. See Flash Memory Sizes for details.
2. This range varies depending on SRAM sizes. See SRAM Ranges for details.
3. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000).
4.3 Flash Memory Map
The flash memory and the flash registers are located at different base addresses as shown
in the following figure. The base address for each is specified in System memory map.
Program flash
Flash configuration field
Program flash base address
Flash memory base address
Registers
Figure 4-1. Flash memory map
The on-chip Flash is implemented in a portion of the allocated Flash range to form a
contiguous block in the memory map beginning at address 0x0000_0000. See Flash
Memory Sizes for details of supported ranges.
Accesses to the flash memory ranges outside the amount of Flash on the device causes
the bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master. Read collision events in which flash memory is accessed while a
flash memory resource is being manipulated by a flash command also generates a bus
error response.
Flash Memory Map
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
106 Freescale Semiconductor, Inc.
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