3.6.3.1 SRAM Sizes
This device contains SRAM which could be accessed by bus masters through the cross-
bar switch. The amount of SRAM for the devices covered in this document is shown in
the following table.
Table 3-30. KL25 SRAM memory size
Device SRAM (KB)
MKL25Z32VFM4 4
MKL25Z64VFM4 8
MKL25Z128VFM4 16
MKL25Z32VFT4 4
MKL25Z64VFT4 8
MKL25Z128VFT4 16
MKL25Z32VLH4 4
MKL25Z64VLH4 8
MKL25Z128VLH4 16
MKL25Z32VLK4 4
MKL25Z64VLK4 8
MKL25Z128VLK4 16
3.6.3.2 SRAM Ranges
The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated
to SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]
This is illustrated in the following figure.
Memories and Memory Interfaces
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
76 Freescale Semiconductor, Inc.
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