9.5 Micro Trace Buffer (MTB)
The Micro Trace Buffer (MTB) provides a simple execution trace capability for the
Cortex-M0+ processor. When enabled, the MTB records changes in program flow
reported by the Cortex-M0+ processor, via the execution trace interface, into a
configurable region of the SRAM. Subsequently an off-chip debugger may extract the
trace information, which would allow reconstruction of an instruction flow trace. The
MTB does not include any form of load/store data trace capability or tracing of any other
information.
In addition to providing the trace capability, the MTB also operates as a simple AHB-Lite
SRAM controller. The system bus masters, including the processor, have read/write
access to all of the SRAM via the AHB-Lite interface, allowing the memory to also be
used to store program and data information. The MTB simultaneously stores the trace
information into an attached SRAM and allows bus masters to access the memory. The
MTB ensures that trace information write accesses to the SRAM take priority over
accesses from the AHB-Lite interface.
The MTB includes trace control registers for configuring and triggering the MTB
functions. The MTB also supports triggering via TSTART and TSTOP control functions
in the MTB DWT module.
9.6 Debug in Low Power Modes
In low power modes in which the debug modules are kept static or powered off, the
debugger cannot gather any debug data for the duration of the low power mode. In the
case that the debugger is held static, the debug port returns to full functionality as soon as
the low power mode exits and the system returns to a state with active debug. In the case
that the debugger logic is powered off, the debugger is reset on recovery and must be
reconfigured once the low power mode is exited.
9.7 Debug & Security
When flash security is enabled, the debug port capabilities are limited in order to prevent
exploitation of secure data. In the secure state the debugger still has access to the status
register and can determine the current security state of the device. In the case of a secure
device, the debugger only has the capability of performing a mass erase operation.
Chapter 9 Debug
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 157
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