NXP Semiconductors KL25 Series - Freescale Semiconductor, Inc

I2Cx_SMB field descriptions (continued)
Field Description
0 SMBus alert response address matching is disabled
1 SMBus alert response address matching is enabled
5
SIICAEN
Second I2C Address Enable
Enables or disables SMBus device default address.
0 I2C address register 2 matching is disabled
1 I2C address register 2 matching is enabled
4
TCKSEL
Timeout Counter Clock Select
Selects the clock source of the timeout counter.
0 Timeout counter counts at the frequency of the bus clock / 64
1 Timeout counter counts at the frequency of the bus clock
3
SLTF
SCL Low Timeout Flag
This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-zero
value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.
NOTE: The low timeout function is disabled when the SLT register's value is zero.
0 No low timeout occurs
1 Low timeout occurs
2
SHTF1
SCL High Timeout Flag 1
This read-only bit sets when SCL and SDA are held high more than clock × LoValue / 512, which indicates
the bus is free. This bit is cleared automatically.
0 No SCL high and SDA high timeout occurs
1 SCL high and SDA high timeout occurs
1
SHTF2
SCL High Timeout Flag 2
This bit sets when SCL is held high and SDA is held low more than clock × LoValue/512. Software clears
this bit by writing a 1 to it.
0 No SCL high and SDA low timeout occurs
1 SCL high and SDA low timeout occurs
0
SHTF2IE
SHTF2 Interrupt Enable
Enables SCL high and SDA low timeout interrupt.
0 SHTF2 interrupt is disabled
1 SHTF2 interrupt is enabled
Memory map and register descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
700 Freescale Semiconductor, Inc.