NXP Semiconductors KL25 Series - Freescale Semiconductor, Inc

The following figure shows the clock formats when CPHA = 1. At the top of the figure,
the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and
bit 8 ending one-half SPSCK cycle after the eighth SPSCK edge. The MSB first and LSB
first lines show the order of SPI data bits depending on the setting in LSBFE. Both
variations of SPSCK polarity are shown, but only one of these waveforms applies for a
specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies
to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies
to the MOSI output pin from a master and the MISO waveform applies to the MISO
output from a slave. The SS OUT waveform applies to the slave select output from a
master (provided MODFEN and SSOE = 1). The master SS output goes to active low
one-half SPSCK cycle before the start of the transfer and goes back high at the end of the
eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.
SS OUT
SS IN
(SLAVE)
(MASTER)
(SLAVE OUT)
MISO
MSB FIRST
LSB FIRST
MOSI
(MASTER OUT)
(MISO OR MOSI)
SAMPLE IN
SPSCK
(CPOL = 1)
SPSCK
(CPOL = 0)
BIT TIME #
(REFERENCE)
BIT 7
BIT 0
BIT 6
BIT 1
BIT 2
BIT 5
BIT 0
BIT 7
BIT 1
BIT 6
1
2 6
7
8
...
...
...
Figure 37-23. SPI Clock Formats (CPHA = 1)
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low,
but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the
first bit of data from the shifter onto the MOSI output of the master and the MISO output
Functional Description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
674 Freescale Semiconductor, Inc.