NXP Semiconductors KL25 Series - System Clock Gating Control Register 6 (SIM_SCGC6)

SIM_SCGC5 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
9
PORTA
Port A Clock Gate Control
This bit controls the clock gate to the Port A module.
0 Clock disabled
1 Clock enabled
8–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
TSI
TSI Access Control
This bit controls software access to the TSI module.
0 Access disabled
1 Access enabled
4–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
LPTMR
Low Power Timer Access Control
This bit controls software access to the Low Power Timer module.
0 Access disabled
1 Access enabled
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)
Address: 4004_7000h base + 103Ch offset = 4004_803Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DAC0
0
RTC
0
ADC0 TPM2 TPM1 TPM0
PIT
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
DMAMUX
FTF
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Chapter 12 System integration module (SIM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 207