NXP Semiconductors KL25 Series - Page 208

SIM_SCGC6 field descriptions
Field Description
31
DAC0
DAC0 Clock Gate Control
This bit controls the clock gate to the DAC0 module.
0 Clock disabled
1 Clock enabled
30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29
RTC
RTC Access Control
This bit controls software access and interrupts to the RTC module.
0 Access and interrupts disabled
1 Access and interrupts enabled
28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
ADC0
ADC0 Clock Gate Control
This bit controls the clock gate to the ADC0 module.
0 Clock disabled
1 Clock enabled
26
TPM2
TPM2 Clock Gate Control
This bit controls the clock gate to the TPM2 module.
0 Clock disabled
1 Clock enabled
25
TPM1
TPM1 Clock Gate Control
This bit controls the clock gate to the TPM1 module.
0 Clock disabled
1 Clock enabled
24
TPM0
TPM0 Clock Gate Control
This bit controls the clock gate to the TPM0 module.
0 Clock disabled
1 Clock enabled
23
PIT
PIT Clock Gate Control
This bit controls the clock gate to the PIT module.
0 Clock disabled
1 Clock enabled
22–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
208 Freescale Semiconductor, Inc.