NXP Semiconductors KL25 Series - MCG Control 3 Register (MCG_C3)

MCG_C2 field descriptions (continued)
Field Description
0 Slow internal reference clock selected.
1 Fast internal reference clock selected.
24.3.3 MCG Control 3 Register (MCG_C3)
Address: 4006_4000h base + 2h offset = 4006_4002h
Bit 7 6 5 4 3 2 1 0
Read
SCTRIM
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
MCG_C3 field descriptions
Field Description
7–0
SCTRIM
Slow Internal Reference Clock Trim Setting
SCTRIM
1
controls the slow internal reference clock frequency by controlling the slow internal reference
clock period. The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing
the binary value increases the period, and decreasing the value decreases the period.
An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, this value is loaded
with a factory trim value.
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this register.
1. A value for SCTRIM is loaded during reset from a factory programmed location .
24.3.4 MCG Control 4 Register (MCG_C4)
NOTE
Reset values for DRST and DMX32 bits are 0.
Address: 4006_4000h base + 3h offset = 4006_4003h
Bit 7 6 5 4 3 2 1 0
Read
DMX32 DRST_DRS FCTRIM SCFTRIM
Write
Reset
0 0 0 x* x* x* x* x*
* Notes:
x = Undefined at reset.•
A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset.•
Memory Map/Register Definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
374 Freescale Semiconductor, Inc.