Table 3-5. Reference links to related information (continued)
Topic Related module Reference
System memory map System memory map
Clocking Clock distribution
Power management Power management
Private Peripheral Bus
(PPB)
ARM Cortex-M0+ core ARM Cortex-M0+ core
3.3.2.1 Interrupt priority levels
This device supports 4 priority levels for interrupts. Therefore, in the NVIC each source
in the IPR registers contains 2 bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ3
0 0 0 0 0 0
IRQ2
0 0 0 0 0 0
IRQ1
0 0 0 0 0 0
IRQ0
0 0 0 0 0 0
W
3.3.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request.
3.3.2.3 Interrupt channel assignments
The interrupt vector assignments are defined in the following table.
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
Table 3-7. Interrupt vector assignments
Address Vector IRQ
1
NVIC
IPR
register
number
2
Source module Source description
ARM Core System Handler Vectors
Table continues on the next page...
Core Modules
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
52 Freescale Semiconductor, Inc.
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