Cypress FM4 Series - Page 258

CHAPTER 7-2: VBAT Domain(A)
258 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
 Allowed transfer combination
Though it should be checked that the TRANS bit in the WTCR0 Register is 0 before the start of a recall
operation or of a save operation, the transfers in a combination with the "o" mark in the following table can
be executed exceptionally.
CREAD
CWRITE
PREAD
PWRITE
BREAD
BWRITE
CREAD



o
o
CWRITE



o
o
PREAD



o
o
PWRITE



o
o
BREAD
o
o
o
o

BWRITE
o
o
o
o

"" indicates that the transfers in that combination can be executed simultaneously.
"" indicates that the transfers in that combination cannot be executed simultaneously.
 Notes on description
In the peripheral manuals of the FM4 Family, a read access and a write access to a register of interface
circuit type 2 or of interface circuit type 3 are defined as follows.
Read access: A recall operation is executed and then data in the buffer is read.
Write access: A recall operation is executed to update the entire buffer. Afterward, the part in the buffer
corresponding to the data of the write access is replaced with such data, and then a save operation is
executed.
 Usage Precautions
− Execute CREAD/CWRITE under the following frequency condition: PCLK2 (APB2 bus clock)  1
MHz
− During the save operation and recall operation, it is prohibited to access any buffer other than the
transfer flag bit (TRANS).
− Set the VB_CLKDIV Register to a value that makes the transfer clock for PREAD, PWRITE,
BREAD and BWRITE generated by dividing PCLK2 become 1 MHz or below.
− When an RTC interrupt occurs, read the transfer completion flag bit (TRANS) of the control register
10 (WTCR10). If it is 1, wait until it becomes “0”, and then access the interrupt flag register.