CHAPTER 7-3: VBAT Domain(B)
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 309
PWRITE/PREAD
Performs a bulk save/recall operation for the registers shown in Table 2-7, which are included in the VBAT
port circuit.
Table 2-7 List of Registers Transferred by PWRITE/PREAD
For the function of each register, see [RTCCLK], which stands for Chapter RTC Clock Control Block in
Timer Part, and 2.6 VBAT I/O Ports and 2.3 32 kHz Oscillation Circuit in this chapter.
The interface circuit type for registers No.1 to No.13 of the VBAT port circuit is type 3.
A save operation is started if 1 is written to VBAT PORT recall control bit (PWRITE) in the WTCR20
Register. This save operation is called a PWRITE operation.
A recall operation is started if 1 is written to VBAT PORT recall control bit (PREAD) in the WTCR20
Register. This recall operation is called a PREAD operation.
The transfer clock is created by dividing PCLK2 by the value of the VB_CLKDIV Register.
The RTC transfers 1 byte of data for one transfer clock.
In one PREAD/PWRITE operation, the RTC transfers data of registers in sequence from No.1 to No.13
shown in Table 2-7.
Since the registers of the VBAT port circuit are 13 bytes in size, the data transfer ends as 13 transfer
clocks elapse.
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