CHAPTER 7-3: VBAT Domain(B)
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 321
Registers of VBAT I/O Ports
List of registers of VBAT I/O ports
Configuration of Registers of VBAT I/O Ports and Method of Accessing those Registers
The interface circuit type for the VBAT I/O port registers is type 3.
For details, see 2.1 Interfacing with Always-on Domain.
The data transfer between a buffer register and a VBAT I/O port register is a batch transfer of data of all
areas.
Update data according to the following procedure.
1. Set the VB_CLKDIV Register to a value that makes the transfer clock become 1 MHz or below.
2. Recall data from the VBAT I/O port retention register to the buffer register.
If 1 is written to VBAT PORT recall control bit(PREAD) in the control register 20(WTCR20), the
recall operation starts and transfer flag bit(TRANS) in the control register 10(WTCR10) becomes
1.
If the recall operation ends, the TRANS bit becomes 0.
3. Modify the content of the buffer register.
The buffer register allows random read access and random write access.
4. Save data in the buffer register to the VBAT I/O port register.
If 1 is written to VBAT PORT save control bit (PWRITE) in the control register 20(WTCR20), the
save operation starts and Transfer flag bit (TRANS) in the control register(WTCR10) becomes 1.
If the save operation ends, the TRANS bit becomes 0.
− Modifying new data in the buffer register alone does not change the state of a VBAT I/O port pin.
To change a VBAT I/O port register value (pin state), execute a save operation to transfer data in
a buffer register corresponding to that VBAT I/O port register to that VBAT I/O port register.
− While transferring data to the data retention register (TRANS bit in the WTCR10 Register is 1), do
not access the buffer register.
− If the Always-on Domain has been reset during the data transfer or the VCC power supply is turned
off, the integrity of the data of the data retention register cannot be guaranteed.
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