Cypress FM4 Series - Page 459

CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 459
Interrupt Signals Output from DMAC
Table 2-2 shows a list of the interrupt signals output from DMAC.
Table 2-2 List of Interrupt Signals from DMAC
Name of Interrupt Signal
Interrupt Factor Register
Interrupt Enable Register
Interrupt Type
DIRQ0
DMACB0:SS[2:0]
DMACB0.CI
ch.0 successful transfer completion interrupt
DMACB0.EI
ch.0 unsuccessful transfer completion interrupt
DIRQ1
DMACB1:SS[2:0]
DMACB1.CI
ch.1 successful transfer completion interrupt
DMACB1.EI
ch.1 unsuccessful transfer completion interrupt
DIRQ2
DMACB2:SS[2:0]
DMACB2.CI
ch.2 successful transfer completion interrupt
DMACB2.EI
ch.2 unsuccessful transfer completion interrupt
DIRQ3
DMACB3:SS[2:0]
DMACB3.CI
ch.3 successful transfer completion interrupt
DMACB3.EI
ch.3 unsuccessful transfer completion interrupt
DIRQ4
DMACB4:SS[2:0]
DMACB4.CI
ch.4 successful transfer completion interrupt
DMACB4.EI
ch.4 unsuccessful transfer completion interrupt
DIRQ5
DMACB5:SS[2:0]
DMACB5.CI
ch.5 successful transfer completion interrupt
DMACB5.EI
ch.5 unsuccessful transfer completion interrupt
DIRQ6
DMACB6:SS[2:0]
DMACB6.CI
ch.6 successful transfer completion interrupt
DMACB6.EI
ch.6 unsuccessful transfer completion interrupt
DIRQ7
DMACB7:SS[2:0]
DMACB7.CI
ch.7 successful transfer completion interrupt
DMACB7.EI
ch.7 unsuccessful transfer completion interrupt
Reference: Interrupt Generation Factors and Clearing (For details, see "4 DMAC Control".)
Interrupt from each channel is generated by the following factors:
− Upon the successful completion of channel transfer, "101" is set to SS[2:0] of the channel. If the
above value is set to SS[2:0] with CI=1 (successful transfer completion interrupt enabled), a
successful transfer completion interrupt occurs.
− Upon the unsuccessful completion of channel transfer, "001", "010", "011" and "100" are set to
SS[2:0] of the channel. If the above value is set to SS[2:0] with EI=1 (unsuccessful transfer
completion interrupt enabled), an unsuccessful transfer completion interrupt occurs.
− The successful transfer completion interrupt and the unsuccessful transfer completion interrupt
undergo logic OR; therefore, if either of the interrupts occurs, an interrupt occurs from the
channel.
Interrupt from each channel can be cleared by writing "000" to SS[2:0].