CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 513
Figure 3-1 Operations of Transfer Number Counter and Transfer Address
Behavior of transfer address count in
the case of increment with
InnerReload
Outer loop counter remain value (ORM)
Inner loop counter remain value (IRM)
Behavior of transfer address count in
the case of increment without
InnerRelaod
4 4 4
4 3 2 1 4 3 2 1 4 3 2 1
Inner loop counter initial value (IIN)
3 2 1
Address outer
reload
(ORL[1]=1,
ORL[2]=1)
Initial value in DES
3
4
4
Start of transfer
Update value from DSTC
(3)
(4)
(4)
Counter outer reload
(ORL[0]=1)
End of transfer
Stride Transfer
If an increase of TW×2 is specified in the SAC[2:0] bits and an increase of TW×4 in the DAC[2:0] bits, a
stride transfer is executed, in which at every transfer, the transfer address increases by TW×2 and by TW
×4 in turn. Figure 3-2 shows an example of executing a transfer with SAC = 000 (increase by TW×1) and
DAC = 010 (increase by TW×2). Using the stride transfer and the chain transfer together facilitates
memory data rearrangement. For its details, see 4.3 Transfer Operation Example 3.
Figure 3-2 Stride Transfer
data2
data3
data0
data1
Source area Destination area
data1
data0
data3
data2
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