Cypress FM4 Series - Page 54

CHAPTER 2-1: Clock
54 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
− When 32k oscillation clock control linkage of VBAT register is disabled
(WTOSCCNT.SOSCNTL=0) and 32k oscillation is disabled (WTOSCCNT.SOSCEX=1), the
setting combination of sub clock mode oscillation of system clock mode control register enabled
(SCM_CTL.SOSCE=1) and sub CSV function of CSV control register enabled
(CSV_CTL.SVSVE=1) is prohibited.
− For details of VBAT RTC, see Chapter VBAT Domain.
− For Release PONR of VBAT domain, see Chapter VBAT Domain 2.4 Power-on circuit.
− If setting to values in VBAT domain, it has to need save operation.
For details of save operation, see Chapter VBAT Domain 2.1 Interface with Always-ON Domain.
− For details of 32k oscillation boost time and transfer clock division, see Chapter VBAT Domain
7.1 VB_CLKDIV Resister and VBAT Domain 7.3 CCS/CCB Resister
− For details of chip power supply control, see Chapter VBAT Domain 3. Chip Power Supply
Control.
− For 32k clock setup procedure, also see another Chapter VBAT Domain 4. Procedure for setting
32 kHz Clock.