Cypress FM4 Series - Page 55

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 55
Figure 4-3 Example of Clock Setup Procedure (Power-on -> High-speed CR Run Mode -> Desired Clock Run Mode)
(TYPE5-M4 products)
Access the Clock Satbilization Wait Time Register
(CSW_TMR). Set the main clock oscillation
stablization wait time.
Access the Interrupt Enable Register (INT_ENR).
Set the oscillation stabilization wait interrupt.
Enable the main clock oscillation in the System Clock
Mode Control Register (SCM_CTL:MOSCE=1).
Ye s
N o
High-speed CR / low-speed CR oscillation stabilization
wait completed. high-speed CR runs as a master clock.
Use the main clock?
with SCM:STR:RCM=SCM_CTL:RCS, changing.
the mode to the selected clcock mode.
Access each bus prescaler register.
BSC_PSR : Base Clock Prescaler
Set bus clock frequency division.
Access the Clock Stabilization Wait Time Register
(CSW_TMR). Set the sub clock oscillation stabilization
wait time.
Access the Interrupt Enable Register (INT_ENR).
Set the oscillation stabilization wait interrupt.
Enable the bus clock oscillation in the System Clock
Mode Control Register (SCM_CTL:SOSCE=1).
Yes
No
Access the PLL Clock Stabilization Wait Time
Register (PSW_TMR). Set the PLL oscillation
stabilization wait time and PLL input clock.
Access the Interrupt Enable Register (INT_ENR).
Set the oscillation satbilization wait interrupt.
Access the PLL control register1, 2 (PLL_CTL1,
PLL_CTL2). Set the PLL multiplication ratio.
Enable the PLL oscillation in the System Clock
Mode Control Register (SCM_CTL:PLLE=1).
No
Access the Interrupt Clear Register (INT_CLR).
Clear the oscillation satbilization wait interrupt factor.
Yes
Use the PLL clock?
Use the sub clock?
Power-on
* Only low-speed CR run
mode is selectable.
Check main clock oscillation stable bit of the System
Clock Mode Status Register (SCM_STR:MORDY=1).
Check sub clock oscillation stable bit of the System
Clock Mode Status Register (SCM_STR:SORDY=1).
Complete waiting for
Waiting for high-speed CR / low-speed CR
oscillation stabilty
Set the master clock switch control bit og the System Clock Mode Control
Register (SCM_CTL:RCS) to desired clock mode.
Use the PLL clock?
No
Yes
* Use high-speed CR clock
i
for the PLL input clock.
APBC0_PSR : APB0 Prescaler
TTC_PSR : Trace Clock Prescaler
Start waiting for
oscillation stability.
Check PLL oscillation stable bit of the System
Clock Mode Status Register (SCM_STR:PLRDY=).
Start waiting for
oscillation stability.
Complete waiting for
oscillation stability.
oscillation stability.
APBC1_PSR : APB1 Prescaler
APBC2_PSR : APB2 Prescaler
Start waiting for
oscillation stability.
Complete waiting for
oscillation stability.