Cypress FM4 Series - Page 56

CHAPTER 2-1: Clock
56 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Figure 4-4 Example of Clock Setup Procedure (Low-speed CR Run Mode -> Desired Clock Run Mode)
(Except TYPE5-M4 products)
Notes:
− Figure 4-4 assumes that settings of the oscillation stabilization wait time, interrupts, PLL
multiplication ratio and bus clock frequency division for each clock have been configured
previously, and they are omitted from the flowchart.
− In the sub clock mode/low-speed CR clock mode, the main clock (CLKMO), high-speed CR clock
(CLKHC), main PLL clock(CLKPLL) is stopped by hardware. So CLKMO/CLKHC/CLKPLL does
not start oscillation only setting oscillation enable bit=1. These oscillations will start by changing
the SCM_CTL:RCS bit with setting oscillation enable bit=1.
− If the main clock/sub clock oscillation stabilization wait times are short and the oscillation
stabilization wait times run out before oscillators stabilize, reset may be applied by the clock
supervisor function.
No
With SCM_STR:RCM=SCM_CTL:RCS, changing
the mode to the selected clock mode.
Y
e
s
No
Set the master clock switch control bit of the
Yes
Yes
No
Low-speed CR run mode
Select the main clock mode?
Main clock mode or PLL run mode
Enable the
PLL oscillation in the System Clock
Mode Control Register (SCM_CTL:PLLE=1).
S
e
l
e
c
t t
he
h
i
gh
-
s
pee
d
CR
r
un
m
ode
?
Select the sub run mode?
Enable the main clock oscillation in the System Clock
Mode Control Register .
PLL oscillation stable bit of the System Clock Mode
Status Register (SCM_STR:PLRDY=1).
Main clock oscillation stable bit of the System Clock
Mode Status Register (SCM_STR:MORDY=1).
Set the master clock switch control bit of the
System Clock Mode Control Register (SCM_CTL:RCS)
to a desired clock mode.
Set sub clock oscillation enabled.
See Figure 4-2
Set the master clock
c
l
o
ck
switch control bit of the
System Clock Mode Control Register (SCM_CTL:RCS)
to a desired clock mode.
Start waiting for
oscillation stability.
Start waiting for
oscillation stability.
Complete waiting for
oscillation stability.
Complete waiting for
oscillation stability.
Complete waiting for
oscillation stability.
Complete waiting for
oscillation stability.
System Clock Mode Control Register (SCM_CTL:RCS)
to a desired clock mode.
Main clock oscillation stable bit of the System Clock
Mode Status Register.