CHAPTER 11: DSTC
550 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
This example illustrates an operation in which relatively complicated Chain Start settings are done. Three
DES are used in this example. Table 4-8 shows the respective values of 1st-DES, 2nd-DES and 3rd-DES.
Transfer Operation Flow
Figure 4-5 shows the transfer operation flow in transfer operation example 5. The Start Triggers of (A), (B),
(D) and (E) in Figure 4-5 indicate HW Start transfers and correspond to the assertion of the transfer
request signal from a peripheral. The Start Triggers of (C), (F) and (G) in Figure 4-5 are Chain Start
Triggers.
Figure 4-5 Operation Flow in Transfer Operation Example 5
0x0000 0x1000 Counter of 1st-DES: (2,2)
(A) Start Trigger to 1st-DES
from peripheral
Wait next trigger
0x0004 0x1004 Counter of 1st-DES:(2,1)
0x2000 0x3000
(B) Start Trigger to 1st-DES
from peripheral
Counter of 2nd-DES:(2,3)
0x2001 0x3001 Counter of 2nd-DES:(2,2)
0x2002 0x3002 Counter of 2nd-DES:(2,1)
0x0000 0x1008 Counter of 1st-DES:(1,2)
(F) Chain Start Trigger
to 2nd-DES from 1st-DES
0x0004 0x100C Counter of 1st-DES:(1,1)
0x2003 0x3000
(E) Start Trigger to 1st-DES
from peripheral
Counter of 2nd-DES:(1,3)
0x2004 0x3001 Counter of 2nd-DES:(1,2)
0x2005 0x3002 Counter of 2nd-DES:(1,1)
(G) Chain Start Trigger
to 3rd-DES from 2nd-DES
0x4000 0x5002 Counter of 3rd-DES(1,2)
End report
Wait next trigger
(D) Start Trigger to 1st-DES
from peripheral
Wait next trigger
0x4000 0x5000
Counter of 3rd-DES(1,1)
(C) Chain start trigger
to 2nd-DES from 1st-DES
*1st-DES close
The DSTC starts the transfer of 1st-DES due to the Start Trigger of (A). The DSTC executes one 32-bit
transfer to the area from address 0x0000 to address 0x1000. The transfer number counter for 1st-DES is
(2,2). According to the setting of CHRS[1:0] of 1st-DES (CHRS[1:0] = 00), the DSTC does not set the
HWINT[n] Register to 1. The DSTC waits for the next Start Trigger.
The DSTC starts the transfer of 1st-DES again due to the Start Trigger of (B). The DSTC executes one
32-bit transfer to the area from address 0x0004 to address 0x1004. The transfer number counter for
1st-DES is (2,1). As CHRS[3:2] of 1st-DES is 10, the Chain Start Trigger for the succeeding transfer of
2nd-DES is issued.
The DSTC starts the transfer of 2nd-DES due to the Start Trigger of (C). The DSTC starts from an 8-bit
transfer to the area from address 0x2000 to address 0x3000. The DSTC executes three times (IIN = 3) of
8-bit transfer successively. The transfer number counter for 2nd-DES starts counting from (2,3) and reads
(2,1) after transfers. According to the setting of CHRS[3:2] of 2nd-DES (CHRS[3:2] = 00), the DSTC does
not set the HWINT[n] Register to 1. The DSTC waits for the next Start Trigger.
The DSTC starts the transfer of 1st-DES again due to the Start Trigger of (D). InnerReload of address is
applied to SA. DA keeps increasing. The DSTC executes one 32-bit transfer to the area from address
0x0000 to address 0x1008. The transfer number counter reads (1,2). According to the setting of
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