CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 555
Procedure to break off a Hardware Transfer of DSTC
This section explains the procedure to break off a hardware transfer of DSTC, by using HW transfer
triggered by ADC as an example.
When performing the HW transfer triggered by ADC, setting DES0.DMSET=1 is required at the first build
of DES before the transfer starts. In order to break off the HW transfer in the middle of the operation and
close the DES, the following procedure can be used.
#1a Write DES0.DV=10 from the CPU
#2a Disable the read skip buffer by writing CFG.RBDIS=1 from the CPU
#3a DSTC waits for a transfer request signal from the ADC. When the transfer request signal is asserted,
the DSTC closes the DES (write DES0.DV=00) and sets “1” to DQMSK[n].
This can avoid occurring subsequent DES open errors.
#4a The CPU waits until DES0.DV=00 can be read.
The transfer can be restarted by the following procedure.
#5a Build the DES again, and then write CFG.RBDIS=0 from the CPU
#6a Write DQMSKCLR=1 from the CPU
To close the DES without the step #3a above (Wait for a transfer request from the ADC), follow the
procedure below.
#1b Disable the transfer request signal of the ADC
For ADC Scan Conversion Transfer: Write ADCR.SCIE=0
For ADC Priority Conversion Transfer: Write ADCR.PCIE=0
#2b Write DES0.DV=10 from the CPU
#3b Disable the read skip buffer by writing CFG.RBDIS=1 from the CPU
#4b Instruct the SW start from the CPU to the DESP performing the HW transfer
(Write DESP to SWTR register)
#5b DSTC closes the DES (Write DES0.DV=00)
In this case, DQMSK[n]=1 is not set.
#6b The CPU waits until DES0.DV=00 can be read.
The transfer can be restarted by the following procedure.
#7b Build the DES again, and tehn write CFG.RBDIS=0 from the CPU
#8b Write DQMSKCLR[n]=1 from the CPU
#9b Write ADCR.SCIE=1 or ADCR.PCIE=1 from the CPU
Note:
− When performed the steps #1b-#6b above, it is possible to execute HW transfer request from the
ADC and the DES close process at the step #3a, before the SW start instruction from the CPU at
step #4b
In this case, the SW start instruction at #4b will be notified as a DES open error. This error can be
ignored because it doesn’t cause any problem.
Also, the step #8b is required for restart since DQMSK[n]=1 is set at the step #3a.
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