Cypress FM4 Series - Page 554

CHAPTER 11: DSTC
554 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
#4 The DQMSK[n] Register has been cleared upon a bus reset. However, it may be set by an HW
Transfer error, a standby transition command or a source specified in DMSET of the DES. Write 1 to
the DQMSKCLR[n] Register to clear the DQMSK[n] Register. If a transfer request signal (DREQ[n])
from a peripheral has been asserted, the clearing of the DQMSK[n] Register by the CPU becomes the
transfer start trigger in #5.
#5 Issues a Start Trigger. In an SW Transfer, write the DESP to the SWTR Register via the CPU. While an
SW Transfer is in progress, no write access can be made to the SWTR Register. In an HW Transfer,
the assertion of the DREQ[n] signal from a peripheral is the Start Trigger.
#6 The DSTC executes a transfer operation according to the DES. The DSTC updates the DES and
returns the transfer status.
#7 Check the transfer status of the DSTC via the CPU. In an SW Transfer, read the SWREQ bit and
SWST bit in the SWTR Register. In an HW Transfer, read the HWINT[n] Register. Read the MONERS
Register to check whether there is a transfer error.
#8 Clear the transfer status of the DSTC via the CPU. In an SW Start transfer, issue an SWCLR
command from the CPU (write "0x10" to the CMD Register) to clear the SWST bit in the SWTR
Register. In an HW Start transfer, write "1" to the HWINTCLR[n] Register to clear the HWINT[n]
Register.
#9, #10 After a transfer error has occurred, issue an ERCLR command (write 0x20 to the CMD Register)
to clear the MONERS Register. If a transfer has been interrupted by an error, rebuild the DES. In an
HW Transfer, peripheral setup may be necessary.
#11 to #13 If it is not necessary to rebuild the DES, issue the next Start Trigger to start a transfer. If it is
necessary to rebuild the DES, rebuild the DES via the CPU, then issue the next Start Trigger to start a
transfer.