Cypress FM4 Series - Page 553

CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 553
Sample Procedure for Controlling Transfer Operation
Figure 4-7 illustrates a sample procedure for controlling the transfer operation of the DSTC. Numbers in
the Figure 4-7 correspond to those used in the explanation after the figure.
Figure 4-7 Sample Procedure for Controlling DSTC Transfer Operation
#2 Setup DSTC registers.
(after Peripheral setup)
#3 Setup DES.
#5 Start trigger.
#6 Transfer operation
#7 Check status register.
#8 Clear status register.
#11 Need DES update?
Y
#9 Transfer error?
#4 Clear DQMSK[n]
#10 Recover error.
#12 New transfer?
#13 End
N
N
Y
Y
N
#1 Start
(DSTC normal state)
#1 This sample procedure starts from the point at which the DSTC is in the normal state. If the DSTC is
not in the normal state, the following processes cannot be executed.
#2 Initialize the control registers of the DSTC. Set the DESTP Register, the CFG Register, the
HWDESP[n] Register and the DREQENB[n] Register to their respective initial values. Write the initial
value to the DREQENB[n] Register after completing the setup of the peripheral. The MONERS
Register is cleared upon a bus reset. However, after the DSTC has been released from the standby
state again, the error record of a previous compulsory end of transfer due to the transition to the
standby state may be kept in the MONERS Register. Use the ERCLR Command (write 0x20 to the
CMD Register) to clear the MONERS Register.
#3 Build in the CPU the DES area to be used by the DSTC.