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Cypress FM4 Series - Page 574

Cypress FM4 Series
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CHAPTER 11: DSTC
574 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
bit[12:10] SAC[2:0] (Source Address Control)
The SAC[2:0] specify the method of updating the transfer source address during a transfer. The DSTC
does not modify the value of this area. The setting is that DES0.DV[1]=1 and DES2 is need to rebuild
(DES2 is not returned to the start value), caused to notify a DES open error from the DSTC.
Value
Function
000
The address is increased by TW×1 at every transfer without InnerReload.
001
The address is increased by TW×1 at every transfer with InnerReload.
010
The address is increased by TW×2 at every transfer without InnerReload.
011
The address is increased by TW×2 at every transfer with InnerReload.
100
The address is increased by TW×4 at every transfer without InnerReload.
101
The transfer address remains unchanged during a transfer.
110
The address is decreased by TW×1 at every transfer without InnerReload.
111
The address is decreased by TW×1 at every transfer with InnerReload.
bit[15:13] DAC[2:0] (Destination Address Control)
The DAC[2:0] specify the method of updating the transfer destination address during a transfer. The
DSTC does not modify the value of this area. The setting is that DES0.DV[1]=1 and DES3 is need to
rebuild (DES3 is not returned to the start value), caused to notify a DES open error from the DSTC.
Value
Function
000
The address is increased by TW×1 at every transfer without InnerReload.
001
The address is increased by TW×1 at every transfer with InnerReload.
010
The address is increased by TW×2 at every transfer without InnerReload.
011
The address is increased by TW×2 at every transfer with InnerReload.
100
The address is increased by TW×4 at every transfer without InnerReload.
101
The transfer address remains unchanged during a transfer.
110
The address is decreased by TW×1 at every transfer without InnerReload.
111
The address is decreased by TW×1 at every transfer with InnerReload.
bit[21:16] CHRS[5:0] (Chain & Return Status)
The CHRS[5:0] bits specify the process to be executed after specified times of transfer have been
executed.
bit
Condition for
selection
Value
Function
CHRS[1:0]
IRM ≠ 1
ORM: ignore
00
No interrupt flag is set. There is no Chain Start.
01
An interrupt flag has been set. There is no Chain Start.
10
No interrupt flag is set. There is a Chain Start in the succeeding DES.
11
No interrupt flag is set. There is a Chain Start in the current DES.
CHRS[3:2]
IRM = 1
ORM ≠ 1
00
No interrupt flag is set. There is no Chain Start.
01
An interrupt flag has been set. There is no Chain Start.
10
No interrupt flag is set. There is a Chain Start in the succeeding DES.
11
No interrupt flag is set. There is a Chain Start in the current DES.
CHRS[5:4]
IRM = 1
ORM = 1
00
No interrupt flag is set. There is no Chain Start.
01
An interrupt flag has been set. There is no Chain Start.
10
No interrupt flag is set. There is a Chain Start in the succeeding DES.
11
11: Setting prohibited (A DES open error occurs.)

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