CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 575
The status of the transfer number counter determines which of CHRS[5:4], CHRS[3:2] and CHRS[1:0] the
DSTC follows when executing the next process after the current DES. If there is an interrupt flag set
instruction, an SW Start Trigger, and a Chain Start Trigger after that SW Start Trigger set the SWST bit to
the SWTR register to 1. An HW Start Trigger, and a Chain Start Trigger after that HW Start Trigger set the
HWINT[n] register to 1. When MODE is 0, as CHRS[1:0] is meaningless, write 00 to it. If MODE is 0 and
CHRS[1:0] is not 00, a DES open error occurs. The DSTC does not modify the value of this area.
bit[22] DMSET (DREQ Mask Set)
For a DES to be started by the HW Start directly from channel n of a peripheral, and a DES to be started
by the Chain Start from the DES mentioned before, with the DMSET bit set to 1, if the DES close process
is not executed, the bit corresponding to that DES in the DQMSK[n] Register is set to 1. The DSTC does
not modify the value of this area.
The DQMSK[n] Register is not set to 1 when the DES close process for an HW Transfer is executed.
The DQMSK[n] Register is set to 1 when the DES close process for an HW Transfer is executed.
bit[23] CHLK (Chain Lock)
The CHLK bit specifies whether to execute the next transfer started by the Chain Start immediately after
the current transfer (Chain Lock) or to enable other transfers to be executed before the next transfer
started by the Chain Start. With the CHLK bit set to 1, if any of CHRS[5], CHRS[3] and CHRS[1] is not 1
(Chain Start selected), a DES open error occurs. The DSTC does not modify the value of this area.
After the current transfer, other transfers can be executed before the Chain Start transfer.
The Chain Start transfer is executed immediately after the current transfer.
bit[25:24] ACK[1:0] (Acknowledge)
The ACK[1:0] bits set the value for adjusting the timing of DSTC outputting the DMA transfer request
acknowledge signal to a peripheral device when the HW Transfer is used. If the HW Transfer is used, set
the ACK[1:0] bits to "01" for a DES to be directly started by the HW Start from a peripheral device. For the
DES started by the Chain Start from the HW Transfer, the DES used in the SW Transfer, and the DES
started by the Chain Start from the SW Transfer, set the ACK[1:0] bits to "00". The DSTC does not modify
the value of this area.
The DSTC does not output the DMA transfer acknowledge signal to the peripheral connected to the
DSTC.
The DSTC outputs the DMA transfer acknowledge signal to the peripheral connected to the DSTC.
bit[27:26] Reserved
Write 00 to this area. If 00 is not written to this area, the DSTC notifies the CPU of a DES open error. The
DSTC does not modify the value of this area.
bit[31:28] PCHK[3:0] (Parity Check)
The PCHK[3:0] bits set the parity (to be called "equation" below) of the DES0 area.
PCHK[3:0] != (DES0[27:24] ^ DES0[23:20] ^ DES0[19:16] ^ DES0[15:12] ^ DES0[11:8] ^ DES0[7:4])
The CPU calculates the parity value while building the DES. The DSTC checks the consistency between
PCHK[3:0] and the value of DES0 area. If a parity error occurs, the DSTC notifies the CPU of a DES open
error. The DSTC does not modify the value of this area. The operation target of PCHK[3:0] is the area of
DES0[27:4], which the DSTC does not modify. A change in the value of DES0[3:0] does not affect the
value of PCHK[3:0].
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